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Rev 0; 12/07
3.3V Margining Clock Oscillator with LVPECL/LVDS Output
General Description
The DS4M125/DS4M133/DS4M200 are margining clock oscillators with LVPECL or LVDS outputs. They are designed to fit in a 5mm x 3.2mm ceramic package with an AT-cut fundamental-mode crystal to form a complete clock oscillator. The circuit can generate the following frequencies and their 5% frequency deviations: 125MHz, 133.33MHz, and 200MHz. The DS4M125/ DS4M133/DS4M200 employ a low-jitter PLL to generate the frequencies. The typical phase jitter is less than 0.9ps RMS from 12kHz to 20MHz. Frequency margining is a circuit operation to change the output frequency to 5% higher or 5% lower than the nominal frequency. Frequency margining is accomplished through the margining select pin, MS. This three-state input pin accepts a three-level voltage signal to control the output frequency. In a low-level state, the output frequency is set to the nominal frequency. When set to a high-level state, the frequency output is set to the nominal frequency plus 5%. When set to the midlevel state, the frequency output is equal to the nominal frequency minus 5%. If left open, the MS pin is pulled low by an internal 100k (nominal) pulldown resistor. The DS4M125/DS4M133/DS4M200 are available with either an LVPECL or LVDS output. The output can be disabled by pulling the OE pin low. When disabled, both OUTP and OUTN levels of the LVPECL driver go to the LVPECL bias voltage, while the output of the LVDS driver is a logical one. The OE input is an active-high logic signal and has an internal 100k pullup resistor. When OE is in a logic-high state, the OUTP and OUTN outputs are enabled. The devices operate from a single 3.3V supply voltage. Frequency Margining: 5% Nominal Clock Output Frequencies: 125MHz, 133.33MHz, and 200MHz Jitter < 0.9ps RMS from 12kHz to 20MHz LVPECL or LVDS Output 3.3V Operating Voltage Operating Temperature Range: -40C to +85C Supply Current: < 100mA at 3.3V Excellent Power-Supply Noise Rejection 5mm x 3.2mm Ceramic LCCC Package Output Enable/Disable
Features
DS4M125/DS4M133/DS4M200
Ordering Information
PART DS4M125P+33 DS4M125D+33 DS4M133P+33 DS4M133D+33 DS4M200P+33 DS4M200D+33 TEMP RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 10 LCCC 10 LCCC 10 LCCC 10 LCCC 10 LCCC 10 LCCC
+Denotes a lead(Pb)-free package. The lead finish is JESD97 category e4 (Au over Ni) and is compatible with both lead-based and lead-free soldering processes.
Applications
Memory Clocks RAID Systems
Pin Configuration and Selector Guide appear at end of data sheet.
Typical Operating Circuit
VCC 0.1F 0.01F OUTP 0.1F 0.01F VCC OUTP 50
DS4M125/ MS DS4M133/ OE DS4M200
GND OUTN
100
DS4M125/ MS DS4M133/ OE DS4M200
GND OUTN
PECL_BIAS AT VCC - 2.0V 50
LVDS OPTION
LVPECL OPTION
________________________________________________________________ Maxim Integrated Products
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3.3V Margining Clock Oscillator with LVPECL/LVDS Output DS4M125/DS4M133/DS4M200
ABSOLUTE MAXIMUM RATINGS
Power-Supply Voltage Range (VCC) .....................-0.3V to +4.0V Continuous Power Dissipation (TA = +70C) ...................330mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+125C Storage Temperature Range ...............................-55C to +85C Soldering Temperature (3 passes max of reflow)..........................................Refer to the IPC/JEDEC J-STD-020 Specification.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = 3.135V to 3.465V, TA = -40C to +85C, unless otherwise noted.) (Notes 1, 2)
PARAMETER Operating Voltage Range Operating Current Inactive Current DS4M125 Frequency DS4M133 DS4M200 Frequency Stability Frequency Stability Over Temperature Initial Tolerance Frequency Change Due to VCC Frequency Change Due to Load Variation Aging (15 Years) Phase Jitter Accumulated Deterministic Jitter Due to Reference Spurs fTOTAL/f O fTEMP/f f INITIAL/f V f VCC/f fLOAD/f O fAGING JRMS Integrated phase RMS; 12kHz to 80MHz, VCC = 3.3V, TA = +25C No margin 155.52MHz output 10kHz Accumulated Deterministic Jitter Due to Power-Supply Noise Startup Time Frequency Switch Time Input-Voltage High (OE) t STRT tSWITCH VIH (Note 5) 0.7 x VCC 100kHz (Note 4) 200kHz (Note 4) 1MHz (Note 4) fO SYMBOL VCC ICC_D ICC_PU ICC_PI ICC_OEZ OUTPUT FREQUENCY SPECIFICATIONS MS = 0, OE = 1 MS = 0, OE = 1 MS = 0, OE = 1 Over temperature range, aging, load, supply, and initial tolerance (Note 3) VCC = 3.3V VCC = 3.3V, TA = +25C VCC = 3.3V 5% 10% variation in termination resistance -7 < 0.9 0.6 12.9 26.3 20.1 6.4 1.0 0.5 VCC ms ms V ps -3 1 +7 -50 -35 20 +3 125 133.33 200 +50 +35 ppm ppm ppm ppm/V ppm ppm ps ps MHz (Note 1) LVDS, output loaded or unloaded LVPECL, output unloaded LVPECL, output loaded VOE = V IL CONDITIONS MIN 3.135 TYP 3.3 52 49 74 52 MAX 3.465 75 70 100 85 mA mA UNITS V
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3.3V Margining Clock Oscillator with LVPECL/LVDS Output
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 3.135V to 3.465V, TA = -40C to +85C, unless otherwise noted.) (Notes 1, 2)
PARAMETER Input-Voltage Low (OE) Input-Leakage High (OE) Input-Leakage Low (OE) Input-Leakage High (MS) Input-Leakage Low (MS) Input Voltage: High Level (MS) SYMBOL VIL ILEAKH ILEAKL ILEAKH ILEAKL VIH (Note 5) OE voltage = VCC OE voltage = GND MS voltage = VCC MS voltage = GND (Note 5) CONDITIONS MIN 0 -5 -20 20 -5 0.75 x VCC + 0.15V 0.25 x VCC + 0.15V TYP MAX 0.3 x VCC +5 -50 50 +5 VCC 0.75 x VCC 0.15V 0.25 x VCC 0.15V UNITS V A A A A V
DS4M125/DS4M133/DS4M200
Input Voltage: Mid Level (MS)
VIM
(Note 5)
V
Input Voltage: Low Level (MS) LVDS Output High Voltage Output Low Voltage Differential Output Voltage Change in VOD for Complementary States Offset Output Voltage Change in VOS for Complementary States Differential Output Impedance
VIL
(Note 5)
0
V
VOH VOL |VOD| |VOD| VOS |VOS| R OLVDS L VSSLVDSO
100 100 100 100 100 100
differential load (Notes 2, 5) differential load (Notes 2, 5) differential load differential load differential load (Note 2) differential load 80 1.125 0.925 250
1.475 425 25 1.275 150 140 40
V V mV mV V mV
OUTN or OUTP shorted to ground and measure the current in the shorting path OUTN and OUTP shorted together and measure the change in ICC 20% to 80% 80% to 20% 45 (Figure 2) (Figure 2) 6.5 175 175
Output Current LLVDSO Output Rise Time (Differential) Output Fall Time (Differential) Duty Cycle Propagation Delay from OE Going LOW to Logical 1 at OUTP Propagation Delay from OE Going HIGH to Output Active tRLVDSO tFLVDSO DCYCLE_LVDS t PA1 t P1A
mA
ps ps 55 200 200 % ns ns
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3.3V Margining Clock Oscillator with LVPECL/LVDS Output DS4M125/DS4M133/DS4M200
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 3.135V to 3.465V, TA = -40C to +85C, unless otherwise noted.) (Notes 1, 2)
PARAMETER LVPECL Output High Voltage (Note 2) Output Low Voltage (Note 2) Differential Voltage Rise Time Fall Time Duty Cycle Propagation Delay from OE Going LOW to Output Three-Stated Propagation Delay from OE Going HIGH to Output Active VOH VOL VDIFF_PECL tR-PECL tF-PECL DCYCLE_PECL t PAZ t PZA (Figure 3) (Figure 3) Output connected to 50 at VCC - 2.0V Output connected to 50 at VCC - 2.0V Output connected to 50 at VCC - 2.0V 20% to 80% 80% to 20% 45 at PECL_BIAS at PECL_BIAS at PECL_BIAS VCC 1.085 VCC 1.825 0.595 0.710 200 200 55 200 200 VCC 0.88 VCC 1.62 V V V ps ps % ns ns SYMBOL CONDITIONS MIN TYP MAX UNITS
Note 1: Limits at -40C are guaranteed by design and are not production tested. Typical values are at +25C and 3.3V, unless otherwise noted. Note 2: AC parameters are guaranteed by design and characterization and are not production tested. Note 3: Frequency stability is calculated as: fTOTAL = fINITIAL + fTEMP + (fVCC x 0.165) + fLOAD + fAGING. Note 4: Supply induced jitter is measured with a 50mVP-P sine wave forced on VCC. Deterministic jitter is calculated by measuring the power of the resulting tone seen on a spectrum analyzer. Note 5: Voltage referenced to ground.
SINGLE-SIDEBAND PHASE NOISE AT fO = fNOM
fM = 10Hz 100Hz 1kHz 10kHz 100kHz 1MHz 10MHz 20MHz SINGLE-SIDEBAND PHASE NOISE AT fO = fNOM (dBc/Hz) 125MHz -70 -100 -118 -118 -124 -142 -150 -150 133.33MHz -75 -105 -121 -122 -126 -141 -150 -150 200MHz -70 -100 -115 -117 -122 -138 -150 -150
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3.3V Margining Clock Oscillator with LVPECL/LVDS Output
Pin Description
PIN 1 2 3 4 5 6 7-10 -- NAME OE MS GND OUTP OUTN VCC N.C. EP Margin Select. Three-level input with a 100k Ground Positive Output for LVPECL or LVDS Negative Output for LVPECL or LVDS Supply Voltage No Connection. Must be floated. Exposed Paddle. The exposed pad must be used for thermal relief. This pad must be connected to ground. FUNCTION Active-High Output Enable. Has an internal pullup 100k resistor. pulldown resistor.
DS4M125/DS4M133/DS4M200
Typical Operating Characteristics
(VCC = +3.3V, TA = +25C, unless otherwise noted.)
FREQUENCY vs. TEMPERATURE
DS4M125/DS4M133/DS4M200 toc01
CURRENT vs. TEMPERATURE
59 57 55 ICC (mA) 53 51 49 47 45
DS4M125/DS4M133/DS4M200 toc02
5 3 fOUT DEVIATION (ppm) 0 -3 -5 -8 -10 fO -13 -15 -40 -20 0 20 40 60 80 TEMPERATURE (C) fO - 5% fO + 5%
-40
-20
0
20
40
60
80
TEMPERATURE (C)
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3.3V Margining Clock Oscillator with LVPECL/LVDS Output DS4M125/DS4M133/DS4M200
VCC
X1 THREESTATE PHASE DET LC-VCO FILTER DIVP DIVOUT OUTSELN OUTDRV OUTN OE OUTP
X2
DS4M125/ DS4M133/ DS4M200
DIVFB
MS
THREELEVEL DECODER
FREQUENCY SELECTION
GND
Figure 1. Functional Diagram
Detailed Description
The DS4M125/DS4M133/DS4M200 consist of an oscillator designed to oscillate with a fundamental-mode crystal and a PLL to synthesize the base frequency with its 5% deviations. The output interface is either LVPECL or LVDS. The 5% frequency deviation is controlled through a three-level margining select (MS) pin. This three-state input pin accepts a three-level voltage signal to control the output frequency. In a low-level state, the output frequency is set to the nominal frequency. When set to a high-level state, the frequency output is set to the
nominal frequency plus 5%. When set to the mid-level state, the frequency output is equal to the nominal frequency minus 5%. The MS pin has an internal 100k pulldown resistor. When the pin is left floating, the devices output a nominal frequency. The devices are available with either LVDS or LVPECL output drivers. When the OE signal is low, the LVPECL output driver is turned off and the output voltage goes to the PECL_BIAS level of VCC - 2.0V, while the LVDS outputs are a logical one. The OE pin has an internal 100k pullup resistor. When the pin is left floating, the device output is active.
0.7 x VCC OE 0.3 x VCC tP1A tPA1 OE
0.7 x VCC 0.3 x VCC tPZA tPAZ PECL_BIAS
OUTP OUTP OUTN PECL_BIAS
OUTN
PECL_BIAS
PECL_BIAS
Figure 2. LVDS Output Timing Diagram When OE Is Enabled and Disabled
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Figure 3. LVPECL Output Timing Diagram When OE Is Enabled and Disabled
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3.3V Margining Clock Oscillator with LVPECL/LVDS Output
Selector Guide
PART DS4M125P+33 DS4M125D+33 DS4M133P+33 DS4M133D+33 DS4M200P+33 DS4M200D+33 FREQUENCY (NOM) (MHz) 125 125 133.33 133.33 200 200 OUTPUT TYPE LVPECL LVDS LVPECL LVDS LVPECL LVDS TOP MARK MEP MED MFP MFD MJP MJD THETA-JA (C/W) 90
Chip Information
SUBSTRATE CONNECTED TO GROUND PROCESS: BiPOLAR SiGe
DS4M125/DS4M133/DS4M200
Thermal Information
+Denotes a lead-free package. The lead finish is JESD97 category e4 (Au over Ni) and is compatible with both lead-based and lead-free soldering processes. A + appears anywhere on the top mark.
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 10 LCCC PACKAGE CODE L1053+H2 DOCUMENT NO. 21-0389
Pin Configuration
TOP VIEW
N.C. N.C.
+
OE 1 6 VCC
MS
2
DS4M125/ DS4M133/ DS4M200
*EP
5
OUTN
GND
3
4
OUTP
N.C.
N.C.
(5.00mm x 3.20mm x 1.49mm)
*EXPOSED PAD
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 7
(c) 2007 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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